According to an embodiment, a DC offset canceller includes a first DA converter, a first adder, an amplifier, a comparator, an averaging circuit, and a successive approximation register. The first DA converter is configured to DA-convert first correction data into a first correction voltage. The first adder is configured to add an input signal and the first correction voltage to output a first added signal. The amplifier is configured to amplify the first added signal to output an amplified signal. The comparator is configured to compare the amplified signal and a reference voltage to output a comparison result. The averaging circuit is configured to receive the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results in a predetermined time period. The successive approximation register is configured to sequentially set each bit of the first correction data based on the majority decision result so that a DC offset in the amplified signal decreases.