Invention Grant
US08380779B2 Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand
有权
用于确定第一操作数和第二操作数的逻辑和是否与第三操作数相同的技术
- Patent Title: Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand
- Patent Title (中): 用于确定第一操作数和第二操作数的逻辑和是否与第三操作数相同的技术
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Application No.: US12474451Application Date: 2009-05-29
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Publication No.: US08380779B2Publication Date: 2013-02-19
- Inventor: Klas M. Bruce , Michael D. Snyder , Ravindraraj Ramaraju , David R. Bearden
- Applicant: Klas M. Bruce , Michael D. Snyder , Ravindraraj Ramaraju , David R. Bearden
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Joanna G. Chiu; David G. Dolezal
- Main IPC: G06F7/50
- IPC: G06F7/50
Abstract:
A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
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