Invention Grant
- Patent Title: Apparatus and method for testing shadow logic
- Patent Title (中): 用于测试阴影逻辑的装置和方法
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Application No.: US12814664Application Date: 2010-06-14
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Publication No.: US08381049B2Publication Date: 2013-02-19
- Inventor: Amit Chhabra
- Applicant: Amit Chhabra
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Hogan Lovells US LLP
- Priority: IN1033/DEL/2010 20100430
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G01R31/28

Abstract:
A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults.
Public/Granted literature
- US20110271156A1 APPARATUS AND METHOD FOR TESTING SHADOW LOGIC Public/Granted day:2011-11-03
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