Invention Grant
- Patent Title: Error correction and recovery in chained memory architectures
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Application No.: US12707421Application Date: 2010-02-17
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Publication No.: US08381059B2Publication Date: 2013-02-19
- Inventor: David R. Resnick
- Applicant: David R. Resnick
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lunberg & Woessner, P.A.
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F13/00 ; G08C25/02 ; H04L1/18 ; H05K7/00
Abstract:
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.
Public/Granted literature
- US20110202813A1 ERROR CORRECTION AND RECOVERY IN CHAINED MEMORY ARCHITECTURES Public/Granted day:2011-08-18
Information query
