Invention Grant
US08381064B2 High density high reliability memory module with power gating and a fault tolerant address and command bus
失效
高密度高可靠性内存模块,具有电源门控和容错地址和命令总线
- Patent Title: High density high reliability memory module with power gating and a fault tolerant address and command bus
- Patent Title (中): 高密度高可靠性内存模块,具有电源门控和容错地址和命令总线
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Application No.: US12827414Application Date: 2010-06-30
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Publication No.: US08381064B2Publication Date: 2013-02-19
- Inventor: Bruce G. Hazelzet
- Applicant: Bruce G. Hazelzet
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
An enhanced four rank enabled buffer device that includes input ports for receiving input data that includes address and command data directed to one or more of up to four ranks of memory devices. The buffer device also includes one or more buffer circuits for driving one or more of the address and command data, a plurality of chip select input lines for selecting between the up to four ranks of memory devices, and a plurality of chip select output lines for accessing the up to four ranks of memory devices. The buffer device further includes a power savings means for causing one or more of the buffer circuits to be in an inactive mode when corresponding chip select input lines are not active. The buffer device is operable to access the up to four ranks of memory devices.
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