Invention Grant
- Patent Title: Error control coding for single error correction and double error detection
- Patent Title (中): 单纠错和双错误检测的错误控制编码
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Application No.: US12588665Application Date: 2009-10-22
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Publication No.: US08381083B2Publication Date: 2013-02-19
- Inventor: Martinus Cornelis Wezelenburg , Thomas Kelshaw Conway
- Applicant: Martinus Cornelis Wezelenburg , Thomas Kelshaw Conway
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
An error correction coding is provided that generates P bits of check data from K M-bit words of payload data. The P bits of check data include an address field A, a bit error indicating field E and an auxiliary field P−(E+A). The address field encodes a set of error addresses which has a cardinality equal to the bit size K of the payload data and providing a one-to-one mapping between values of the address field and the locations of a single bit error within the payload data. The bit error indicating field indicates if a bit error is present. The auxiliary field is a minimum size bit vector such that together with the address field and the bit area indicating field it provides a checksum for a systematic code for the payload data with a minimum Hamming distance serving to provide either single error correction capability or single error correction and double error detection capability.
Public/Granted literature
- US20110099451A1 Error control coding for single error correction and double error detection Public/Granted day:2011-04-28
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