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US08381155B1 Vertical interconnect patterns in multi-layer integrated circuits 有权
多层集成电路中的垂直互连图案

Vertical interconnect patterns in multi-layer integrated circuits
Abstract:
A method of generating valid vertical interconnect positions for a multiple layer integrated circuit including multiple layers stacked vertically above one another and having a bonding interface between at least one pair of layers. The interface is formed by the coupling of a pair of conductive bond patterns formed on facing surfaces of the pair of layers. The method includes defining a candidate transformation origin, defining a sub-region which tessellates across the patterns, applying a predetermined transformation to the patterns at the bonding interface, determining the validity of the candidate transformation origin in dependence on coincidence of at least a subset of the patterns with the transformed patterns, selecting a valid transformation origin, and defining a set of valid vertical interconnect positions associated with the valid transformation origin at positions in the bonding interface where the original and transformed patterns coincided with each other.
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