Invention Grant
- Patent Title: Vertical interconnect patterns in multi-layer integrated circuits
- Patent Title (中): 多层集成电路中的垂直互连图案
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Application No.: US13200831Application Date: 2011-10-03
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Publication No.: US08381155B1Publication Date: 2013-02-19
- Inventor: David A. Fick , Ronald G. Dreslinski , Trevor N. Mudge , David T. Blaauw , Dennis M. Sylvester
- Applicant: David A. Fick , Ronald G. Dreslinski , Trevor N. Mudge , David T. Blaauw , Dennis M. Sylvester
- Applicant Address: US MI Ann Arbor
- Assignee: The Regents of the University of Michigan
- Current Assignee: The Regents of the University of Michigan
- Current Assignee Address: US MI Ann Arbor
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of generating valid vertical interconnect positions for a multiple layer integrated circuit including multiple layers stacked vertically above one another and having a bonding interface between at least one pair of layers. The interface is formed by the coupling of a pair of conductive bond patterns formed on facing surfaces of the pair of layers. The method includes defining a candidate transformation origin, defining a sub-region which tessellates across the patterns, applying a predetermined transformation to the patterns at the bonding interface, determining the validity of the candidate transformation origin in dependence on coincidence of at least a subset of the patterns with the transformed patterns, selecting a valid transformation origin, and defining a set of valid vertical interconnect positions associated with the valid transformation origin at positions in the bonding interface where the original and transformed patterns coincided with each other.
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