Invention Grant
- Patent Title: Verification computer product, method, and apparatus
- Patent Title (中): 验证计算机产品,方法和设备
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Application No.: US13020615Application Date: 2011-02-03
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Publication No.: US08381158B2Publication Date: 2013-02-19
- Inventor: Hiroki Miyaoka , Seiichiro Yamaguchi , Tsuyoshi Sakata
- Applicant: Hiroki Miyaoka , Seiichiro Yamaguchi , Tsuyoshi Sakata
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2010-033014 20100217
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F17/10

Abstract:
A recording medium stores a verification program that causes a computer to execute detecting from a model circuit, a first circuit representing junction of a source region and a substrate region and including a junction resistance and a junction capacitance, a second circuit parallel to the first circuit, representing junction of a drain region and the substrate region, and including a junction resistance and a junction capacitance equivalent to the junction resistance and capacitance of the first circuit, and a connection resistance connecting the circuits and a substrate electrode; calculating, using the junction resistances and connection resistance, a first coefficient indicating impact of the junction resistances and connection resistance on amplitude variation; calculating, using the junction capacitances and connection resistance, a second coefficient indicating impact of the junction capacitances and connection resistance on phase variation; correcting the junction capacitances using a sum of the coefficients; and outputting a correction result.
Public/Granted literature
- US20110202895A1 VERIFICATION COMPUTER PRODUCT, METHOD, AND APPARATUS Public/Granted day:2011-08-18
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