Invention Grant
- Patent Title: Method of semiconductor integrated circuit, and computer readable medium
- Patent Title (中): 半导体集成电路方法及计算机可读介质
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Application No.: US12978307Application Date: 2010-12-23
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Publication No.: US08381159B2Publication Date: 2013-02-19
- Inventor: Keiichirou Kondou , Hiroyuki Tsuchiya
- Applicant: Keiichirou Kondou , Hiroyuki Tsuchiya
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2009-292712 20091224
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
A design method of a semiconductor integrated circuit sets an area having apices of opposing corners of a position of a start point logic cell and a position of an end point logic cell to a repeater search area, adds free area information to the repeater search area, sets a drive boundary in the repeater search area based on a drive ability of the start point logic cell, searches a repeater candidate that can be arranged in an area of the drive boundary based on the free area information, calculates a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched, and determines a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated.
Public/Granted literature
- US20110161904A1 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE MEDIUM Public/Granted day:2011-06-30
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