Invention Grant
- Patent Title: System and method for monotonic partial order reduction
- Patent Title (中): 用于单调部分阶次降低的系统和方法
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Application No.: US12367140Application Date: 2009-02-06
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Publication No.: US08381226B2Publication Date: 2013-02-19
- Inventor: Vineet Kahlon , Chao Wang , Aarti Gupta
- Applicant: Vineet Kahlon , Chao Wang , Aarti Gupta
- Applicant Address: US NJ Princeton
- Assignee: NEC Laboratories America, Inc.
- Current Assignee: NEC Laboratories America, Inc.
- Current Assignee Address: US NJ Princeton
- Agent Joseph Kolodka; James Bitetto
- Main IPC: G06F11/36
- IPC: G06F11/36

Abstract:
A system and method for analyzing concurrent programs that guarantees optimality in the number of thread inter-leavings to be explored. Optimality is ensured by globally constraining the inter-leavings of the local operations of its threads so that only quasi-monotonic sequences of threads operations are explored. For efficiency, a SAT/SMT solver is used to explore the quasi-monotonic computations of the given concurrent program. Constraints are added dynamically during exploration of the concurrent program via a SAT/SMT solver to ensure quasi-montonicity for model checking.
Public/Granted literature
- US20090204968A1 SYSTEM AND METHOD FOR MONOTONIC PARTIAL ORDER REDUCTION Public/Granted day:2009-08-13
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