Invention Grant
- Patent Title: Compliant off-chip interconnects for use in electronic packages and fabrication methods
- Patent Title (中): 适用于电子封装和制造方法的片外互连
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Application No.: US13435977Application Date: 2012-03-30
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Publication No.: US08382489B2Publication Date: 2013-02-26
- Inventor: Karan Kacker , Suresh K. Sitaraman
- Applicant: Karan Kacker , Suresh K. Sitaraman
- Applicant Address: US GA Atlanta
- Assignee: Georgia Tech Research Corporation
- Current Assignee: Georgia Tech Research Corporation
- Current Assignee Address: US GA Atlanta
- Agency: Thomas|Horstemeyer, LLP.
- Main IPC: H01R12/00
- IPC: H01R12/00

Abstract:
Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.
Public/Granted literature
- US20120192418A1 Compliant Off-Chip Interconnects for Use in Electronic Packages and Fabrication Methods Public/Granted day:2012-08-02
Information query