Invention Grant
- Patent Title: Integrated high-K/metal gate in CMOS process flow
- Patent Title (中): CMOS工艺流程中集成的高K /金属栅极
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Application No.: US13186572Application Date: 2011-07-20
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Publication No.: US08383502B2Publication Date: 2013-02-26
- Inventor: Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
- Applicant: Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763

Abstract:
A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
Public/Granted literature
- US20110275212A1 Integrated High-K/Metal Gate in CMOS Process Flow Public/Granted day:2011-11-10
Information query
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