Invention Grant
- Patent Title: Tunneling transistor suitable for low voltage operation
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Application No.: US12425962Application Date: 2009-04-17
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Publication No.: US08384122B1Publication Date: 2013-02-26
- Inventor: Chenming Hu , Anupama Bowonder , Pratik Patel , Daniel Chou , Prashant Majhi
- Applicant: Chenming Hu , Anupama Bowonder , Pratik Patel , Daniel Chou , Prashant Majhi
- Applicant Address: US CA Oakland
- Assignee: The Regents of the University of California
- Current Assignee: The Regents of the University of California
- Current Assignee Address: US CA Oakland
- Agency: Withrow & Terranova, PLLC
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.
Information query
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