Invention Grant
US08384148B2 Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling
有权
制造具有改进的电容耦合的浮栅非易失性MOS半导体存储器件的方法
- Patent Title: Method of making a floating gate non-volatile MOS semiconductor memory device with improved capacitive coupling
- Patent Title (中): 制造具有改进的电容耦合的浮栅非易失性MOS半导体存储器件的方法
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Application No.: US11317679Application Date: 2005-12-22
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Publication No.: US08384148B2Publication Date: 2013-02-26
- Inventor: Paolo Tessariol , Roberto Bez , Marcello Mariani
- Applicant: Paolo Tessariol , Roberto Bez , Marcello Mariani
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Priority: EP04425936 20041222; EP04425937 20041222
- Main IPC: H01L29/788
- IPC: H01L29/788

Abstract:
A method of making a non-volatile MOS semiconductor memory device includes a formation step, in a semiconductor material substrate, of STI isolation regions (shallow trench isolation) filled by field oxide and of memory cells separated each other by said STI isolation regions. The memory cells include a gate electrode electrically isolated from said semiconductor material substrate by a first dielectric layer, and the gate electrode includes a floating gate self-aligned to the STI isolation regions. The method includes a formation phase of said floating gate exhibiting a substantially saddle shape including a concavity; the formation step of said floating gate includes a deposition step of a first conformal conductor material layer.
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