Provided is a package structure of a semiconductor device, capable of further reducing a planar size. The semiconductor device comprises a first package 2 embedding a first element 1, and a second package 4 stacked on and fixed to the first package while internally housing a second element 3. The first package 2 includes a lead frame 5 and a metallization wiring 6. The metallization wiring 6 is formed by resin-molding the first package 2 using a transfer lead frame having the metallization wiring 6 arranged on a base substrate, and, after the resin molding, removing the base substrate to leave the metallization wiring 6 on a removing surface of a molded resin in a transferred manner, while allowing a peripheral region of the metallization wiring 6 to be exposed on the side of and in flush relation with the removing surface of the molded resin so as to serve as an external terminal 6a. The first element 1 is mounted on the external terminal 6a of the metallization wiring 6in at least partially overlapped relation therewith, through an insulator layer 8, and electrically connected to the lead frame 5 and the metallization wiring 6.