Invention Grant
- Patent Title: Test pad structure, a pad structure for inspecting a semiconductor chip and a wiring subtrate for a tape package having the same
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Application No.: US12457775Application Date: 2009-06-22
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Publication No.: US08384407B2Publication Date: 2013-02-26
- Inventor: So-Young Lim , Sang-Heul Lee
- Applicant: So-Young Lim , Sang-Heul Lee
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2008-0060345 20080625
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G01R31/02

Abstract:
A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads arranged in a second row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a third row next to the second row.
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