Consistent with the present disclosure, clock-and-data recovery (CDR) circuitry and driver circuitry are provided on a chip that is separate from the driver circuitry, thereby reducing the amount of power consumed by the driver circuitry and simplifying system design. In one example, timing of the ERZ signals is controlled by a feedback loop that adjusts the phase of a data carrying signal relative to a clock signal, such that the phase has a desired value. Timing of the ERZ signals may thus be adjusted to minimize errors.