Invention Grant
- Patent Title: Replacing single-cut via into multi-cut via in semiconductor integrated circuit design
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Application No.: US13428286Application Date: 2012-03-23
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Publication No.: US08386970B2Publication Date: 2013-02-26
- Inventor: Toshiaki Ueda
- Applicant: Toshiaki Ueda
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Foley & Lardner LLP
- Priority: JP2005-360907 20051214
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
According an aspect of the invention, there is provided a design support system of a semiconductor integrated circuit includes: a first unit configured to determine a wiring path by calculating wiring resource consuming information for carrying out a connection through a multi-cut via in case that the connection is carried out through the multi-cut via in a wiring region having a plurality of layers; and a second unit configured to replacing a single-cut via into the multi-cut via.
Public/Granted literature
- US20120180007A1 REPLACING SINGLE-CUT VIA INTO MULTI-CUT VIA IN SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN Public/Granted day:2012-07-12
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