Invention Grant
- Patent Title: Methods for making multi-chip packaging using an interposer
- Patent Title (中): 使用插入片进行多芯片封装的方法
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Application No.: US12955816Application Date: 2010-11-29
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Publication No.: US08387240B2Publication Date: 2013-03-05
- Inventor: Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
- Applicant: Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Konrad Raynes Davda & Victor LLP
- Agent Alan S. Raynes
- Main IPC: H01K3/10
- IPC: H01K3/10

Abstract:
In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.
Public/Granted literature
- US20110067236A1 MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS Public/Granted day:2011-03-24
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