To include a comparison circuit that generates comparison results by comparing plural pieces of data simultaneously read via data lines with expected values, an AND gate that activates a first determination signal in response to a fact that at least one of the comparison results indicates a mismatch, and an OR gate that activates a second determination signal in response to a fact that all the comparison results indicate a mismatch. With this arrangement, when a detection test of a defective address is performed in a wafer state, a defect of a column selection line can be detected.