Invention Grant
- Patent Title: Memory devices and methods for managing error regions
- Patent Title (中): 用于管理错误区域的内存设备和方法
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Application No.: US13405554Application Date: 2012-02-27
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Publication No.: US08392771B2Publication Date: 2013-03-05
- Inventor: Joe M. Jeddeloh
- Applicant: Joe M. Jeddeloh
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/00

Abstract:
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.
Public/Granted literature
- US20120159270A1 MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS Public/Granted day:2012-06-21
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