Invention Grant
US08392857B2 Automated circuit design process for generation of stability constraints for generically defined electronic system with feedback
有权
自动电路设计过程,用于产生具有反馈的一般定义的电子系统的稳定性约束
- Patent Title: Automated circuit design process for generation of stability constraints for generically defined electronic system with feedback
- Patent Title (中): 自动电路设计过程,用于产生具有反馈的一般定义的电子系统的稳定性约束
-
Application No.: US12631672Application Date: 2009-12-04
-
Publication No.: US08392857B2Publication Date: 2013-03-05
- Inventor: Sunderarajan S. Mohan , Almir Mutapcic , Ricardo Antonio Oliva
- Applicant: Sunderarajan S. Mohan , Almir Mutapcic , Ricardo Antonio Oliva
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Agent Judith A. Szepesi
- Main IPC: G06F9/455
- IPC: G06F9/455

Abstract:
A method is described that involves accepting a description of an electronic system having feedback. The method further includes expressing a real root of the electronic system's transfer function and expressing a real part of a complex root of the electronic system's transfer function. The method further includes expressing a time parameter as a maximum of the real root and the real part of a complex root. The method further involves expressing a settling time of the electronic system with the time parameter and using the settling time to automatically generate a design for the electronic system.
Public/Granted literature
Information query