Invention Grant
US08392888B2 Method of translating n to n instructions employing an enhanced extended translation facility 有权
使用增强的扩展翻译设施翻译n到n个指令的方法

Method of translating n to n instructions employing an enhanced extended translation facility
Abstract:
A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining backward compatibility with existing systems. The enhanced Extended-Translation Facility 2 (ETF2) instruction set introduces a new operand in an unused field (M3) that facilitates a change in the original instruction format and its intended function. With the ETF2-Enhancement Facility installed, a value of zeros in the M3 field indicates that instruction operation is to continue as originally defined. When a nonzero value is coded in the M3 field a new function is carried out. The assembler accommodates the changes by making the new M3 field optional when coding the instructions. If the M3 field is not coded, the assembler defaults to providing zeros in the M3 field (as found in the original instruction format), and backward compatible operation is provided.
Information query
Patent Agency Ranking
0/0