Invention Grant
- Patent Title: Method of manufacturing wiring substrate
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Application No.: US12579726Application Date: 2009-10-15
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Publication No.: US08394225B2Publication Date: 2013-03-12
- Inventor: Tatsuya Nakamura , Tomoko Yamada
- Applicant: Tatsuya Nakamura , Tomoko Yamada
- Applicant Address: JP Nagano-Shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-Shi
- Agency: Rankin, Hill & Clark LLP
- Priority: JP2008-267094 20081016
- Main IPC: B32B38/10
- IPC: B32B38/10

Abstract:
Two stacked bodies, each having a metal layer provided on a first metallic foil with carrier via a first insulating layer, are prepared. The first metallic foil with carrier has a metallic foil provided on a carrier plate via a peeling layer. A joined body is formed by jointing the stacked bodies such that the carrier plates are joined via a joining layer. First conductor patterns are formed by patterning the metal layers on both sides of the joined body. Second metallic foils with carrier are provided to the first conductor patterns of the joined body such that the first conductor patterns are opposed to the metallic foils via second insulating layers. Two substrates are formed by peeling the carrier plates with carrier from the peeling layers. Second conductor patterns which are connected electrically to the first conductor patterns are formed from the metallic foils of the substrate.
Public/Granted literature
- US20100096078A1 METHOD OF MANUFACTURING WIRING SUBSTRATE Public/Granted day:2010-04-22
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