Invention Grant
- Patent Title: Semiconductor chip stacked body and method of manufacturing the same
- Patent Title (中): 半导体芯片堆叠体及其制造方法
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Application No.: US12626069Application Date: 2009-11-25
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Publication No.: US08394678B2Publication Date: 2013-03-12
- Inventor: Kei Murayama , Akinori Shiraishi , Mitsuhiro Aizawa
- Applicant: Kei Murayama , Akinori Shiraishi , Mitsuhiro Aizawa
- Applicant Address: JP Nagano-Shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-Shi
- Agency: Rankin, Hill & Clark LLP
- Priority: JP2008-305187 20081128; JP2009-010828 20090121; JP2009-149116 20090623; JP2009-266485 20091124
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/02 ; H01L23/22 ; H01L23/24 ; H01L23/52

Abstract:
A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a cubic form in which a portion of the conductive connecting material except an end portion located on an external device side and all surfaces of semiconductor chip is sealed by the resin and the end portion of the conductive connecting material located on the external device side is exposed from the cubic form. A conductive bonding wire connects the end portions of the conductive connecting materials and the connection terminal respectively. A resin sealing material seals the plurality of chip sealing bodies, the conductive bonding wire, and the wiring substrate.
Public/Granted literature
- US20100133677A1 SEMICONDUCTOR CHIP STACKED BODY AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2010-06-03
Information query
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