Invention Grant
US08394680B2 Layout for semiconductor device and method of fabricating the semiconductor device
有权
用于半导体器件的布局和制造半导体器件的方法
- Patent Title: Layout for semiconductor device and method of fabricating the semiconductor device
- Patent Title (中): 用于半导体器件的布局和制造半导体器件的方法
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Application No.: US12650364Application Date: 2009-12-30
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Publication No.: US08394680B2Publication Date: 2013-03-12
- Inventor: Ho Hyuk Lee
- Applicant: Ho Hyuk Lee
- Applicant Address: KR Icheon-Si
- Assignee: Hynix Semiconductor Inc
- Current Assignee: Hynix Semiconductor Inc
- Current Assignee Address: KR Icheon-Si
- Priority: KR10-2009-0070476 20090731
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L21/44 ; H01L23/52 ; H01L27/108 ; H01L29/94

Abstract:
In a layout for a semiconductor device, each active region comprises a first active region, a right active region on the right side of the first active region, a left active region on the left side of the first active region, an upper active region on the upper side of the first active region and a lower active region on the lower side of the first active region, wherein the first active region, the right active region, the left active region, the upper active region and the lower active region each have an inclined portion having a bit-line contact region; and first and second portions having a storage node contact region, first and second ends formed on left and right ends of the inclined portion at a predetermined tilt angle with respect to the inclined portion, the active region being intersected by two word lines and one bit line.
Public/Granted literature
- US20110024870A1 LAYOUT FOR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE Public/Granted day:2011-02-03
Information query
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