Invention Grant
US08394689B2 Semiconductor memory device with stacked gate including charge storage layer and control gate and method of manufacturing the same
有权
具有包括电荷存储层和控制栅极的堆叠栅极的半导体存储器件及其制造方法
- Patent Title: Semiconductor memory device with stacked gate including charge storage layer and control gate and method of manufacturing the same
- Patent Title (中): 具有包括电荷存储层和控制栅极的堆叠栅极的半导体存储器件及其制造方法
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Application No.: US13426664Application Date: 2012-03-22
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Publication No.: US08394689B2Publication Date: 2013-03-12
- Inventor: Yoshiko Kato , Mitsuhiro Noguchi
- Applicant: Yoshiko Kato , Mitsuhiro Noguchi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McCelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-333306 20071225
- Main IPC: H01L29/72
- IPC: H01L29/72
Abstract:
A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.
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