Method for manufacturing semiconductor device, and semiconductor device

Invention Grant

US08394693B2 Method for manufacturing semiconductor device, and semiconductor device 有权

Title translation: 半导体装置的制造方法以及半导体装置

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Patent Title: Method for manufacturing semiconductor device, and semiconductor device
Patent Title (中): 半导体装置的制造方法以及半导体装置
Application No.: US13354344

Application Date: 2012-01-20
Publication No.: US08394693B2

Publication Date: 2013-03-12
Inventor: Kazushi Fujita
Applicant: Kazushi Fujita
Applicant Address: JP Yokohama
Assignee: Fujitsu Semiconductor Limited
Current Assignee: Fujitsu Semiconductor Limited
Current Assignee Address: JP Yokohama
Agency: Fujitsu Patent Center
Priority: JP2008-179964 20080710
Main IPC: H01L21/8238
IPC: H01L21/8238

Method for manufacturing semiconductor device, and semiconductor device

Abstract:

A semiconductor device includes a first MISFET having a first conduction type channel and formed on a semiconductor substrate; a second MISFET having a second conduction type channel and formed on the semiconductor substrate; a first strain film having a first sign strain that covers a region where the second MISFET is disposed; and a second strain film having a second sign strain that covers a region where the first MISFET is disposed. In the semiconductor device, an edge of the second strain film closer to the second MISFET overlaps with part of the first strain film; and the second strain film at a portion where the second strain film overlaps with the first strain film and at a portion extending from the portion, is thinner than the second strain film at a portion that covers the first MISFET.

Abstract(Chinese):

半导体器件包括具有第一导电型沟道并形成在半导体衬底上的第一MISFET; 具有第二导电型沟道并形成在所述半导体衬底上的第二MISFET; 具有覆盖所述第二MISFET的区域的第一符号应变的第一应变膜; 以及具有覆盖所述第一MISFET的区域的第二符号应变的第二应变膜。在半导体器件中，更靠近第二MISFET的第二应变膜的边缘与第一应变膜的一部分重叠; 并且第二应变膜在第二应变膜与第一应变膜重叠的部分和从该部分延伸的部分处的第二应变膜在覆盖第一MISFET的部分处比第二应变膜薄。

Public/Granted literature

US20120115291A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Public/Granted day:2012-05-10

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS