Invention Grant
- Patent Title: Method for obtaining a layout design for an existing integrated circuit
- Patent Title (中): 获得现有集成电路布局设计的方法
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Application No.: US13104986Application Date: 2011-05-11
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Publication No.: US08394721B2Publication Date: 2013-03-12
- Inventor: Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
- Applicant: Ming-Teng Hsieh , Yi-Nan Chen , Hsien-Wen Liu
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L21/311
- IPC: H01L21/311

Abstract:
A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.
Public/Granted literature
- US20120289048A1 Method for obtaining a layout design for an existing integrated circuit Public/Granted day:2012-11-15
Information query
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