A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.