Invention Grant
- Patent Title: Nanoscale floating gate
- Patent Title (中): 纳米级浮动门
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Application No.: US13231371Application Date: 2011-09-13
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Publication No.: US08395202B2Publication Date: 2013-03-12
- Inventor: Gurtej S. Sandhu , D. V. Nirmal Ramaswamy
- Applicant: Gurtej S. Sandhu , D. V. Nirmal Ramaswamy
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/788 ; H01L21/8247
Abstract:
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.
Public/Granted literature
- US20120001248A1 METHODS OF FORMING NANOSCALE FLOATING GATE Public/Granted day:2012-01-05
Information query
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