Invention Grant
- Patent Title: DMOS transistor and method of manufacturing the same
- Patent Title (中): DMOS晶体管及其制造方法
-
Application No.: US12680012Application Date: 2008-09-26
-
Publication No.: US08395210B2Publication Date: 2013-03-12
- Inventor: Yasuhiro Takeda , Seiji Otake , Shuichi Kikuchi
- Applicant: Yasuhiro Takeda , Seiji Otake , Shuichi Kikuchi
- Applicant Address: JP Ora-gun US AZ Phoenix
- Assignee: SANYO Semiconductor Co., Ltd.,Semiconductor Components Industries, LLC
- Current Assignee: SANYO Semiconductor Co., Ltd.,Semiconductor Components Industries, LLC
- Current Assignee Address: JP Ora-gun US AZ Phoenix
- Agency: Morrison & Foerster LLP
- Priority: JP2007-255092 20070928
- International Application: PCT/JP2008/068113 WO 20080926
- International Announcement: WO2009/041741 WO 20090402
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/336
Abstract:
The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A′. A first body layer 17A′ is formed by this first ion implantation. The first body layer 17A′ is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A′ in the first corner portion 14C1 is higher than that of a conventional transistor.
Public/Granted literature
- US20100193865A1 DMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2010-08-05
Information query
IPC分类:
