Invention Grant
US08395224B2 Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes
有权
具有非重叠PMOS晶体管和非重叠NMOS晶体管的线栅极电平交叉耦合晶体管器件相对于栅电极的方向
- Patent Title: Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes
- Patent Title (中): 具有非重叠PMOS晶体管和非重叠NMOS晶体管的线栅极电平交叉耦合晶体管器件相对于栅电极的方向
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Application No.: US12753758Application Date: 2010-04-02
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Publication No.: US08395224B2Publication Date: 2013-03-12
- Inventor: Scott T. Becker , Jim Mali , Carole Lambert
- Applicant: Scott T. Becker , Jim Mali , Carole Lambert
- Applicant Address: US CA Los Gatos
- Assignee: Tela Innovations, Inc.
- Current Assignee: Tela Innovations, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Martine Penilla Group, LLP
- Main IPC: H01L27/088
- IPC: H01L27/088

Abstract:
A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.
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