Invention Grant
- Patent Title: Method of stacking semiconductor chips including forming an interconnect member and a through electrode
- Patent Title (中): 堆叠包括形成互连部件和贯通电极的半导体芯片的方法
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Application No.: US12656616Application Date: 2010-02-04
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Publication No.: US08395269B2Publication Date: 2013-03-12
- Inventor: Masaya Kawano , Koji Soejima , Nobuaki Takahashi , Yoichiro Kurita , Masahiro Komuro , Satoshi Matsui
- Applicant: Masaya Kawano , Koji Soejima , Nobuaki Takahashi , Yoichiro Kurita , Masahiro Komuro , Satoshi Matsui
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2005-349794 20051202
- Main IPC: H01L21/50
- IPC: H01L21/50

Abstract:
A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.
Public/Granted literature
- US20100144091A1 Semiconductor device and method of manufacturing the same Public/Granted day:2010-06-10
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