Invention Grant
US08395412B2 Calibration circuit, semiconductor device including the same, and data processing system
有权
校准电路,包括相同的半导体器件和数据处理系统
- Patent Title: Calibration circuit, semiconductor device including the same, and data processing system
- Patent Title (中): 校准电路,包括相同的半导体器件和数据处理系统
-
Application No.: US13067644Application Date: 2011-06-16
-
Publication No.: US08395412B2Publication Date: 2013-03-12
- Inventor: Fumiyuki Osanai , Hiroki Fujisawa
- Applicant: Fumiyuki Osanai , Hiroki Fujisawa
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-176270 20070704
- Main IPC: H03K17/16
- IPC: H03K17/16

Abstract:
A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.
Public/Granted literature
- US20110248742A1 Calibration circuit, semiconductor device including the same, and data processing system Public/Granted day:2011-10-13
Information query