Invention Grant
- Patent Title: Logic circuit without enhancement mode transistors
- Patent Title (中): 没有增强型晶体管的逻辑电路
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Application No.: US12980264Application Date: 2010-12-28
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Publication No.: US08395413B2Publication Date: 2013-03-12
- Inventor: Haoyang Yu
- Applicant: Haoyang Yu
- Applicant Address: US OR Hillsboro
- Assignee: Triquint Semiconductor, Inc.
- Current Assignee: Triquint Semiconductor, Inc.
- Current Assignee Address: US OR Hillsboro
- Agency: Schwabe Williamson & Wyatt
- Main IPC: H03K17/16
- IPC: H03K17/16
Abstract:
Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Some embodiments include a circuit having a logic circuit with an input stage and an output stage; a heterojunction bipolar transistor configured to provide a first switched supply voltage to power components of the input stage; and a depletion mode field effect transistor configured to provide a second switched supply voltage to power components of the output stage. Other embodiments may also be described and claimed.
Public/Granted literature
- US20120161812A1 LOGIC CIRCUIT WITHOUT ENHANCEMENT MODE TRANSISTORS Public/Granted day:2012-06-28
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