In a clear period, transistors NT38 and PT38 turn on and state retention nodes HQ and H/Q are cleared to an L level and an H level, respectively. In this clear period, a transistor NT21 is off. Consequently, a precharge node PS maintains itself at an H level. Thus, transistors PT31 and NT32 are off, thereby preventing a short circuit from occurring in a clear period. A short circuit is also prevented from occurring in a preset period.