A singled-ended, successive approximation register analog-to-digital converter convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits. The SAR ADC comprises SAR logic, a resistive network, multiple switches, and first and second LSB capacitors. The switches also comprises two sets of switches coupled to the resistive network, each set of switches is configured to couple a selected tap to each of the first and second LSB capacitors. When determining the lower order bits, the SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of both taps changes by a decreasing amount with each succeeding bit being determined.