A circuit for a flat panel display includes an image data storage and processing block, a display and timing controller block, an image pixel matrix containing a multitude of row and column arranged pixel elements, one or more controlled row and column driver blocks, and a tagged multi line addressing (TMLA) pixel element display operation. That TMLA operation comprises a decomposition of image data by searching all lines of an image for groups of identical lines by tagging each of these lines with a unique code and thus decomposes image data into multi line and single line domain data in such a way, that lines with matching tags, indicating their common and identical contents, are outputted as image data into related groups of the multi line domain with no left over residual image data and thus the related groups in the single line domain data are all zeroes.