Invention Grant
- Patent Title: Input/output circuit
- Patent Title (中): 输入/输出电路
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Application No.: US13289696Application Date: 2011-11-04
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Publication No.: US08395870B2Publication Date: 2013-03-12
- Inventor: Masato Maede
- Applicant: Masato Maede
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2009-132824 20090602
- Main IPC: H02H9/00
- IPC: H02H9/00 ; E02H1/00

Abstract:
An output transistor bias generation circuit which applies a bias voltage to one of two NMOS transistors constituting an output circuit having a stack structure, includes diode-connected NMOS transistors provided between an external connection pad connected to an external signal line having a voltage higher than a power supply voltage of an LSI circuit, and the gate of an NMOS transistor, diode-connected NMOS transistors provided between the gate of the NMOS transistor and a ground line, a diode-connected NMOS transistor provided between the power supply line and the gate of the NMOS transistor, and a capacitor-connected NMOS transistor provided between the gate of the NMOS transistor and the ground line.
Public/Granted literature
- US20120049939A1 INPUT/OUTPUT CIRCUIT Public/Granted day:2012-03-01
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