Invention Grant
US08395937B2 Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
有权
包括具有分段位线架构的存储器阵列和控制和/或操作相同方法的集成电路
- Patent Title: Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
- Patent Title (中): 包括具有分段位线架构的存储器阵列和控制和/或操作相同方法的集成电路
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Application No.: US13166291Application Date: 2011-06-22
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Publication No.: US08395937B2Publication Date: 2013-03-12
- Inventor: David Fisch , Michel Bron
- Applicant: David Fisch , Michel Bron
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wilmer Cutler Pickering Hale and Dorr LLP
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.
Public/Granted literature
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