Invention Grant
- Patent Title: Increased DRAM-array throughput using inactive bitlines
- Patent Title (中): 使用不稳定位线增加DRAM阵列吞吐量
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Application No.: US13082785Application Date: 2011-04-08
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Publication No.: US08395947B2Publication Date: 2013-03-12
- Inventor: Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
- Applicant: Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle America, Inc.
- Current Assignee: Oracle America, Inc.
- Current Assignee Address: US CA Redwood Shores
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Main IPC: G11C7/10
- IPC: G11C7/10

Abstract:
A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to a proximate I/O line that is in use. For example, unused bitlines located on the top and bottom of the memory array may be used to route data signals to adjacent local I/O lines. In particular, the data signals can be placed on unused local I/O lines which are associated with adjacent bitline sense amplifiers. The resulting increased communication bandwidth can overcome the constraints imposed by the limited number of local I/O lines in the memory device without appreciably increasing the chip size, power consumption, or cost.
Public/Granted literature
- US20110261637A1 INCREASED DRAM-ARRAY THROUGHPUT USING INACTIVE BITLINES Public/Granted day:2011-10-27
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