A memory device includes a plurality of memory arrays, each memory array being coupled to an input data bus and an output data bus, a clock generator that generates an internal clock signal to form at least one transfer cycle to control timing of data transfer to and from the plurality of memory arrays, and a controller that controls read and write operations from and to the plurality of memory arrays. In one embodiment, the controller receives a command word containing at least a first command and a second command and executes the first and second command on the same transfer cycle.