Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.