Invention Grant
US08397187B2 Verifying the error bound of numerical computation implemented in computer systems
失效
验证在计算机系统中实现的数值计算的误差界限
- Patent Title: Verifying the error bound of numerical computation implemented in computer systems
- Patent Title (中): 验证在计算机系统中实现的数值计算的误差界限
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Application No.: US12766163Application Date: 2010-04-23
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Publication No.: US08397187B2Publication Date: 2013-03-12
- Inventor: Jun Sawada
- Applicant: Jun Sawada
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Eustus D. Nelson; Robert C. Rolnik
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F17/15 ; G06F17/17 ; G01R35/00 ; G01D3/00

Abstract:
A verification tool receives a finite precision definition for an approximation of an infinite precision numerical function implemented in a processor in the form of a polynomial of bounded functions. The verification tool receives a domain for verifying outputs of segments associated with the infinite precision numerical function. The verification tool splits the domain into at least two segments, wherein each segment is non-overlapping with any other segment and converts, for each segment, a polynomial of bounded functions for the segment to a simplified formula comprising a polynomial, an inequality, and a constant for a selected segment. The verification tool calculates upper bounds of the polynomial for the at least two segments, beginning with the selected segment and reports the segments that violate a bounding condition.
Public/Granted literature
- US20110264990A1 VERIFYING THE ERROR BOUND OF NUMERICAL COMPUTATION IMPLEMENTED IN COMPUTER SYSTEMS Public/Granted day:2011-10-27
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