Invention Grant
US08399336B2 Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer
有权
用于制造具有在较高成本的有源电路层之前堆叠的较低成本有源电路层的3D集成电路器件的方法
- Patent Title: Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer
- Patent Title (中): 用于制造具有在较高成本的有源电路层之前堆叠的较低成本有源电路层的3D集成电路器件的方法
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Application No.: US12194211Application Date: 2008-08-19
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Publication No.: US08399336B2Publication Date: 2013-03-19
- Inventor: Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
- Applicant: Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Gibbons Gutman Bongini & Bianco PL
- Agent Stephen Bongini
- Main IPC: H01L21/30
- IPC: H01L21/30
Abstract:
A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
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