Invention Grant
US08399344B2 Method for adjusting the threshold voltage of a gate stack of a PMOS device
有权
用于调整PMOS器件的栅极堆叠的阈值电压的方法
- Patent Title: Method for adjusting the threshold voltage of a gate stack of a PMOS device
- Patent Title (中): 用于调整PMOS器件的栅极堆叠的阈值电压的方法
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Application No.: US12898911Application Date: 2010-10-06
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Publication No.: US08399344B2Publication Date: 2013-03-19
- Inventor: Dieter Pierreux , Vladimir Machkaoutsan , Jan Willem Maes
- Applicant: Dieter Pierreux , Vladimir Machkaoutsan , Jan Willem Maes
- Applicant Address: NL Almere
- Assignee: ASM International N.V.
- Current Assignee: ASM International N.V.
- Current Assignee Address: NL Almere
- Agency: Preti Flaherty Believeau & Pachios LLP
- Main IPC: H01L21/28
- IPC: H01L21/28

Abstract:
A method for fabricating a semiconductor device comprising a gate stack of a gate dielectric and a gate electrode, the method including forming a gate dielectric layer over a semiconductor substrate the gate dielectric layer being a metal oxide or semimetal oxide having a first electronegativity; forming a dielectric VT adjustment layer, the dielectric VT adjustment layer being a metal oxide or semimetal oxide having a second electronegativity; and forming a gate electrode over the gate dielectric layer and the VT adjustment layer; wherein the Effective Work Function of said gate stack is tuned to a desired value by tuning the thickness and composition of the dielectric VT adjustment layer and wherein the second electronegativity value is higher than both the first electronegativity value and the electronegativity of Al2O3.
Public/Granted literature
- US20110081775A1 METHOD FOR ADJUSTING THE THRESHOLD VOLTAGE OF A GATE STACK OF A PMOS DEVICE Public/Granted day:2011-04-07
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