Invention Grant
- Patent Title: Stacked semiconductor package and method for manufacturing the same
- Patent Title (中): 堆叠半导体封装及其制造方法
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Application No.: US12972963Application Date: 2010-12-20
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Publication No.: US08399355B2Publication Date: 2013-03-19
- Inventor: Kwon Whan Han
- Applicant: Kwon Whan Han
- Applicant Address: KR Kyoungki-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Kyoungki-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2007-0109766 20071030
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/00

Abstract:
A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips, each semiconductor chip having a first face, a second face opposite to the first face, and a circuit part. A through portion passes through the first and second faces of the semiconductor chip. A recess part is formed in a portion of the second face where the second face and the through portion meet. A through electrode is electrically connected to the circuit part and is disposed inside of the through portion. A connection member is disposed in the recess part to electrically connect the through electrodes of adjacent stacked semiconductor chips. And the semiconductor chip module is mounted to a substrate. The stacked semiconductor package prevents both gaps between semiconductor chips and misalignment of the through electrode.
Public/Granted literature
- US20110092024A1 STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2011-04-21
Information query
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