Invention Grant
- Patent Title: Thin film transistor and manufacturing method thereof
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Application No.: US13336292Application Date: 2011-12-23
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Publication No.: US08399887B2Publication Date: 2013-03-19
- Inventor: Yoshiharu Hirakata , Yukie Nemoto
- Applicant: Yoshiharu Hirakata , Yukie Nemoto
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Robinson Intellectual Property Law Office, P.C.
- Agent Eric J. Robinson
- Priority: JP2003-076640 20030319
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
The present invention provides a structure of the TFT in which a current-voltage characteristic can be improved. The present invention refers to a thin film transistor comprising a lamination layer wherein a first conductive film, a first insulating film and a second conductive film are sequentially laminated, a semiconductor film formed so as to be in contact with the side surface of the lamination layer, and a third conductive film covering the semiconductor film through a second insulating film. The first conductive film and the second conductive film are a source electrode and a drain electrode, and a region which is in contact with the first insulating film and the third conductive film is a channel forming region in semiconductor film, and the third conductive film is a gate electrode.
Public/Granted literature
- US20120112196A1 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF Public/Granted day:2012-05-10
Information query
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