Invention Grant
US08400845B2 Column address strobe write latency (CWL) calibration in a memory system
有权
存储器系统中的列地址选通写延迟（CWL）校准
- Patent Title: Column address strobe write latency (CWL) calibration in a memory system
- Patent Title (中): 存储器系统中的列地址选通写延迟（CWL）校准
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Application No.: US12985481Application Date: 2011-01-06
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Publication No.: US08400845B2Publication Date: 2013-03-19
- Inventor: Lydia M. Do , William M. Zevin
- Applicant: Lydia M. Do , William M. Zevin
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Main IPC: G11C7/10
- IPC: G11C7/10
Abstract:
Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.
Public/Granted literature
- US20120176850A1 COLUMN ADDRESS STROBE WRITE LATENCY (CWL) CALIBRATION IN A MEMORY SYSTEM Public/Granted day:2012-07-12
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